| CPC G06N 3/10 (2013.01) [G06F 7/5443 (2013.01); G06F 12/0238 (2013.01); G06F 2207/4824 (2013.01); G06F 2212/72 (2013.01)] | 18 Claims |
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1. A non-volatile memory device, comprising:
a memory array of a plurality of non-volatile memory cells connected along bit lines and word lines, each of the memory cells configured to store a bit of a multi-bit valued weight of a layer of a neural network;
a plurality of sense amplifiers each connected one of the bit lines and configured to provide a binary output value;
a plurality of adders connected to receive output values of the sense amplifiers and to receive a mode signal, the adders configurable to perform an accumulation operation of one of a plurality of settable levels of precision in response to the mode signal; and
one or more control circuits connected to the memory array and the adders, the one or more control circuits configured to:
perform an in-array multiplication between a multi-bit valued input of the layer of the neural network with the weight of the layer of neural by applying the bits of the input as binary inputs along word lines of the memory array;
supply the mode signal to configure the adders to set the level of precision for the adders; and
perform an accumulation operation by the adders of the output values of the sense amplifiers in response to the in-array multiplication at the set level of precision.
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