US 12,079,710 B2
Scalable neural network accelerator architecture
Adam Fuks, Sunnyvale, CA (US); Paul Kimelman, Alamo, CA (US); Franciscus Petrus Widdershoven, Eindhoven (NL); Brian Christopher Kahne, Austin, TX (US); and Xiaomin Lu, Austin, TX (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Dec. 31, 2020, as Appl. No. 17/139,318.
Prior Publication US 2022/0207332 A1, Jun. 30, 2022
Int. Cl. G06N 3/063 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06N 3/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a two dimensional array of registers, wherein each of the registers is configured to store data;
a compute block comprising a plurality of data processing pipeline circuits, each comprising a plurality of processing devices, wherein each of the processing devices comprises first and second storage elements, and wherein each of the processing devices is configured to process data in its first and second storage elements to produce an output;
a first circuit for selecting read sub arrays of the array, wherein each of the read sub arrays comprises RH rows of registers and RW columns of registers, wherein RH and RW are integers; and
a first load circuit for loading data from registers of the selected read sub arrays into respective first storage elements of the compute block.