US 12,079,661 B2
Processing device and method for managing tasks thereof
Wongyu Shin, Seongnam-si (KR); Miock Chi, Seongnam-si (KR); Hongyun Kim, Seongnam-si (KR); Jinwook Oh, Seongnam-si (KR); and Juyeong Yoon, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Oct. 20, 2023, as Appl. No. 18/491,695.
Claims priority of application No. 10-2022-0146444 (KR), filed on Nov. 4, 2022; application No. 10-2022-0146533 (KR), filed on Nov. 4, 2022; and application No. 10-2022-0146543 (KR), filed on Nov. 4, 2022.
Prior Publication US 2024/0152391 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/48 (2006.01); G06F 9/38 (2018.01)
CPC G06F 9/4881 (2013.01) [G06F 9/3838 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A neural processing device comprising:
processing circuitry; and
task managing circuitry operably coupled to the processing circuitry,
wherein the task managing circuitry is configured to cause:
receiving a plurality of tasks;
storing the plurality of received tasks in a dependency check waiting memory;
determining whether reference tasks which a task in the dependency check waiting memory depends on are completed based on a dependency of the task in the dependency check waiting memory and a dependency check memory region, wherein the dependency of the task in the dependency check waiting memory represents a list of tasks which have to be completed for the task in the dependency check waiting memory to be transferred to the processing circuitry and the dependency check memory region represents whether reference tasks which tasks in the dependency check waiting memory depend on are completed;
transferring the task in the dependency check waiting memory to a process waiting memory in response to determining that reference tasks which the task in the dependency check waiting memory depends on are completed;
transferring tasks in the process waiting memory to the processing circuitry; and
updating the dependency check memory region in response to a signal indicating that a task processed by the processing circuitry is completed.