US 12,079,631 B2
Method and system for hardware-assisted pre-execution
Sanyam Mehta, Bloomington, MN (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed on Jun. 2, 2023, as Appl. No. 18/328,099.
Application 18/328,099 is a continuation of application No. 17/412,200, filed on Aug. 25, 2021, granted, now 11,687,344.
Prior Publication US 2023/0315471 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01)
CPC G06F 9/3814 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30065 (2013.01); G06F 9/321 (2013.01); G06F 9/38 (2013.01); G06F 9/3802 (2013.01); G06F 9/5016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer system, comprising:
one or more processors; and
a memory coupled to the one or more processors and storing instructions which, when executed by the one or more processors, cause the processors to:
set, in a first entry for a first instruction in a data structure, a first prefetch region identifier with a first current value of a global counter; and
responsive to a head pointer of the data structure reaching the first entry:
determine, based on a non-zero value for the first prefetch region identifier, that the first entry is not available to be allocated; and
advance the head pointer to a next entry in the data structure, which renders a load associated with the first entry as a non-blocking load.