US 12,079,630 B2
Array processor having an instruction sequencer including a program state controller and loop controllers
Matthew Brandon Gately, Austin, TX (US); Eric Jonathan Deal, Austin, TX (US); Mark Willard Johnson, Austin, TX (US); and Sebastian Ahmed, San Diego, CA (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Jun. 28, 2021, as Appl. No. 17/361,240.
Prior Publication US 2022/0414049 A1, Dec. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/345 (2018.01); G06F 9/32 (2018.01)
CPC G06F 9/3455 (2013.01) [G06F 9/325 (2013.01)] 21 Claims
OG exemplary drawing
 
15. A method of processing array data arranged in a memory, the method comprising:
decoding a macro-instruction into commands;
dispatching the commands into data pipeline circuitry;
updating loop counters of loop controllers according to the macro-instruction; and
updating a program counter according to the macro-instruction and states of the loop controllers,
wherein the array data are specified with programmable per-dimension size and stride values,
wherein updating the loop counters of the loop controllers comprises using a begin flag corresponding to a first loop controller of the loop controllers and using an end flag corresponding to the first loop controller, the begin flag and the end flag being included in the macro-instruction.