US 12,079,627 B1
Predicated compare-exchange-shuffle instruction for parallel processor
Himanshu Pradeep Aswani, Bangalore (IN); Mithil Ramteke, Bangalore (IN); Venkata Prema Sai Sravan Patchala, Bangalore (IN); and Sridhar Kandimalla, Bengaluru (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 23, 2023, as Appl. No. 18/189,115.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30029 (2013.01) [G06F 9/30032 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processor-implemented method for executing a hardware intrinsic programming instruction, comprising:
performing at least one Boolean operation in combination with at least one permutation operation in response to the hardware intrinsic programming instruction comprising a single predicated compare-exchange-shuffle programming instruction; and
outputting a sub-sorted list after the performing of the at least one Boolean operation in combination with the at least one permutation operation.