US 12,079,516 B2
Host-preferred memory operation
Tony M. Brewer, Plano, TX (US); and Dean E. Walker, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/823,314.
Prior Publication US 2024/0069800 A1, Feb. 29, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 9/38 (2018.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0607 (2013.01); G06F 9/3877 (2013.01); G06F 3/0679 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an interface to receive a request from a host;
an accelerator; and
a memory side cache with processing circuitry configured to:
receive a first memory operation from a host;
determine that the first memory operation, from the host via the interface, corresponds to a cache set based on an address of the first memory operation;
receive a second memory operation from the accelerator;
determine that the second memory operation corresponds to the cache set;
enqueue the first memory operation in a host queue of the cache set;
enqueue the second memory operation in an internal request queue of the cache set; and
execute the first memory operation and the second memory operation as each is dequeued, wherein dequeuing the host queue is prioritized over dequeuing the internal request queue.