CPC G06F 3/0632 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a memory structure comprising non-volatile memory cells; and
a control circuit in communication with the memory structure, wherein the control circuit is configured to:
access a single-bit per cell (SLC) program mode parameter that specifies whether to operate in a first SLC program mode or to operate in a second SLC program mode;
program a first set of the memory cells to a single bit per cell using a first set of sub-clock durations that are shared with a multi-bit per cell (MLC) program mode in response to the mode parameter specifying the first SLC program mode, wherein the first set of sub-clock durations includes a first time duration for each particular sub-clock in a set of the sub-clocks; and
program a second set of the memory cells to a single bit per cell using a second set of sub-clock durations in response to the mode parameter specifying the second SLC program mode, wherein the second set of sub-clock durations includes a second time duration for each particular sub-clock in the set of the sub-clocks, wherein the second time duration is shorter than the first time duration for each particular sub-clock in the set of the sub-clocks.
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