| CPC G06F 3/0625 (2013.01) [G06F 3/0644 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] | 20 Claims |
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1. A memory system comprising:
a memory device including a memory cell array divided into a plurality of memory banks; and
a memory controller configured to send read requests or write requests to the memory device for inputting data to or outputting data from the memory banks of the memory cell array, respectively, and to send the read requests so as to be separated from the write requests based on a read-write switching point,
wherein the memory controller is configured to
in a first turn of input/output (I/O) requests including the read requests or the write requests, set a near switching point before the read-write switching point based on a number of I/O requests processed in the first turn from among the I/O requests,
block scheduling at least one of first bank requests, between the near switching point and the read-write switching point for at least one first preliminary I/O request to be scheduled in the first turn, the at least one of the first bank requests indicating state switching of the memory banks, and
schedule at least one of second bank requests so as to be issued between the near switching point and the read-write switching point, for second preliminary I/O requests to be scheduled in a second turn after the read-write switching point, the at least one of the second bank requests indicating state switching of the memory banks.
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