| CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 11/1048 (2013.01); G11C 29/42 (2013.01)] | 20 Claims |
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14. A method of operating a memory system including a semiconductor memory device and a memory controller configured to control the semiconductor memory device, the method comprising:
performing a refresh operation with respect to a plurality of memory cells included in a memory cell array of the semiconductor memory device while the memory cell array is in a memory refresh maintenance state;
generating, in the semiconductor memory device, error information by monitoring an error in data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation;
providing the error information from the semiconductor memory device to the memory controller;
providing the error information from the semiconductor memory device to the memory controller; and
correcting the error in the data stored in the memory cell array using an error correction code (ECC) circuit included in the memory controller based on the error information.
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