US 12,079,486 B2
High-throughput low-latency hybrid memory module
Aws Shallal, Cary, NC (US); Micheal Miller, Raleigh, NC (US); and Stephen Horn, Raleigh, NC (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jun. 22, 2023, as Appl. No. 18/339,812.
Application 18/339,812 is a continuation of application No. 17/339,683, filed on Jun. 4, 2021, granted, now 11,687,247.
Application 17/339,683 is a continuation of application No. 16/535,814, filed on Aug. 8, 2019, granted, now 11,036,398, issued on Jun. 15, 2021.
Application 16/535,814 is a continuation of application No. 16/042,374, filed on Jul. 23, 2018, granted, now 10,379,752, issued on Aug. 13, 2019.
Application 16/042,374 is a continuation of application No. 14/883,155, filed on Oct. 14, 2015, granted, now 10,031,677, issued on Jul. 24, 2018.
Prior Publication US 2023/0409205 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/00 (2006.01); G06F 12/0802 (2016.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G11C 5/04 (2006.01); G11C 11/00 (2006.01); G11C 14/00 (2006.01); G06F 11/14 (2006.01); G11C 7/10 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0611 (2013.01); G06F 3/065 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0685 (2013.01); G06F 11/00 (2013.01); G06F 12/0802 (2013.01); G06F 12/1441 (2013.01); G06F 13/1673 (2013.01); G11C 5/04 (2013.01); G11C 11/005 (2013.01); G11C 14/0009 (2013.01); G06F 11/14 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/205 (2013.01); G11C 7/1051 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a command buffer device, the method comprising:
receiving one or more local commands from a non-volatile memory controller,
controlling access, by access logic of the command buffer device, to one or more control setting registers by the non-volatile memory controller in a first control mode, wherein a portion of the control setting registers comprises a protected register space;
receiving one or more access commands from the non-volatile memory controller to access the one or more control setting registers; and
interpreting, by an access engine of the command buffer device, the one or more access commands to provide access to the protected register space in the first control mode.