US 12,079,484 B2
Random reads using multi-port memory and on-chip memory blocks
Abhishek Kumar Jain, Ghaziabad (IN); Henri Fraisse, Sunnyvale, CA (US); and Dinesh D. Gaitonde, Fremont, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Aug. 3, 2023, as Appl. No. 18/230,117.
Application 18/230,117 is a continuation of application No. 17/184,458, filed on Feb. 24, 2021, granted, now 11,720,255.
Prior Publication US 2023/0409204 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a first value and an associated first identifier from a first memory;
hashing the first identifier to produce a memory block identifier for a memory block of a second memory;
routing, based on the memory block identifier, a read request to the memory block of the second memory;
receiving a property from the memory block of the second memory based on the read request;
updating the first value received from the first memory based on the received property; and
storing the updated first value in the first memory.