a memory bank comprising a plurality of banks that comprise memory cells; and

a PIM (processing in memory) circuit comprising a plurality of PIM blocks, each of the PIM blocks comprising an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit,

wherein the plurality of PIM blocks comprises a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank,

wherein the address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank,

wherein the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank,

wherein the first internal row address and the second internal row address indicate different rows,

wherein the address generating unit of the first PIM block is configured to generate a first internal column address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal column address for the at least one second bank, and

wherein the first internal column address and the second internal column address indicate respective columns different from each other.