| CPC G06F 3/0611 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 19 Claims |
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1. A memory device comprising:
a plurality of plane groups comprising:
a first plane group comprising a first plane of the memory device; and
a second plane group comprising a second plane of the memory device;
a first input/output (I/O) interface configured to access the first plane group;
a second I/O interface configured to access the second plane group;
a multiplexer circuit coupled to the first I/O interface and the second I/O interface, the multiplexer circuit to:
enable the first I/O interface to access the first plane group and the second plane group, and
enable the second I/O interface to access the first plane group and the second plane group; and
a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel, the controller to perform operations comprising:
transmitting, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane; and
transmitting, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane, wherein the first memory access operation and the second memory access operation are executed concurrently.
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