US 12,079,475 B1
Ferroelectric memory chiplet in a multi-dimensional packaging
Amrita Mathuriya, Portland, OR (US); Christopher B. Wilkerson, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Debo Olaosebikan, San Francisco, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Apr. 13, 2021, as Appl. No. 17/229,743.
Application 17/229,743 is a continuation in part of application No. 16/428,885, filed on May 31, 2019, granted, now 11,043,472.
Int. Cl. G06F 3/06 (2006.01); G06F 12/0817 (2016.01); G06N 20/00 (2019.01)
CPC G06F 3/061 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 12/0828 (2013.01); G06N 20/00 (2019.01); G06F 2212/621 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a first die comprising a switch and a first plurality of input-output transceivers, wherein the first die is on the substrate;
a memory die on the first die via a memory interface, wherein the first die includes a memory controller to manage data traffic to the memory die;
a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers, and wherein the second die is on the memory die; and
a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os, and wherein the third die in on the second die.