US 12,079,470 B2
Streaming engine with fetch ahead hysteresis
Matthew Pierson, Murphy, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 19, 2021, as Appl. No. 17/379,345.
Application 17/379,345 is a continuation of application No. 16/860,151, filed on Apr. 28, 2020, granted, now 11,068,164.
Application 16/860,151 is a continuation of application No. 16/279,757, filed on Feb. 19, 2019, granted, now 10,642,490, issued on May 5, 2020.
Application 16/279,757 is a continuation of application No. 15/384,416, filed on Dec. 20, 2016, granted, now 10,209,887, issued on Feb. 19, 2019.
Prior Publication US 2021/0349635 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 13/14 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 9/3004 (2013.01); G06F 9/30047 (2013.01); G06F 9/30076 (2013.01); G06F 9/3016 (2013.01); G06F 9/32 (2013.01); G06F 9/3802 (2013.01); G06F 9/383 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 13/14 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit device comprising:
a memory controller configured to couple to a memory and at least one processing unit that includes:
an address generator configured to generate, in response to an instruction from the at least one processing unit, a set of addresses to retrieve a set of data from the memory using a set of loops;
data storage configured to the set of data retrieved from the memory; and
fetch circuitry that includes:
a set of registers each configured to store a respective loop count of a respective loop of the set of loops;
a first set of computation circuitry configured to determine an amount of data in a pending portion of the set of data based on the loop counts stored in the set of registers;
a second set of computation circuitry configured to determine an amount of available space in the data storage; and
a fetch controller coupled to the first set of computation circuitry and the second set of computation circuitry and configured to provide fetch commands to retrieve the set of data from the memory such that:
when the amount of data in the pending portion of the set of data is less than or equal to the amount of available space in the data storage, a set of fetch commands associated with the pending portion is provided to the memory;
when the amount of data in the pending portion of the set of data is greater than the amount of available space in the data storage and the amount of available space in the data storage is greater than a hysteresis value, a subset of the set of fetch commands associated with the pending portion having an amount based on the hysteresis value is provided to the memory; and
when the amount of data in the pending portion of the set of data is greater than the amount of available space in the data storage and the amount of available space in the data storage is less than the hysteresis value, providing of the set of fetch commands associated with the pending portion is delayed until the amount of available space in the data storage at least meets the hysteresis value.