US 12,079,350 B2
Secure public key acceleration
Timothy R. Paaske, Cupertino, CA (US); Mitchell D. Adler, Los Gatos, CA (US); Conrad Sauerwald, Mountain View, CA (US); Fabrice L. Gautier, San Jose, CA (US); and Shu-Yi Yu, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Apr. 17, 2023, as Appl. No. 18/301,860.
Application 18/301,860 is a continuation of application No. 17/081,276, filed on Oct. 27, 2020, granted, now 11,630,903.
Application 17/081,276 is a continuation of application No. 16/691,900, filed on Nov. 22, 2019, granted, now 10,853,504, issued on Dec. 1, 2020.
Application 16/691,900 is a continuation of application No. 16/138,670, filed on Sep. 21, 2018, granted, now 10,521,596, issued on Dec. 31, 2019.
Application 16/138,670 is a continuation of application No. 15/860,314, filed on Jan. 2, 2018, granted, now 10,114,956, issued on Oct. 30, 2018.
Application 15/860,314 is a continuation of application No. 15/372,697, filed on Dec. 8, 2016, granted, now 9,892,267, issued on Feb. 13, 2018.
Application 15/372,697 is a continuation of application No. 14/498,820, filed on Sep. 26, 2014, granted, now 9,547,778, issued on Jan. 17, 2017.
Prior Publication US 2023/0385427 A1, Nov. 30, 2023
Int. Cl. G06F 21/60 (2013.01); G06F 21/32 (2013.01); G06F 21/62 (2013.01); G06F 21/71 (2013.01); G09C 1/00 (2006.01); H04L 9/08 (2006.01); H04L 9/30 (2006.01); H04L 9/32 (2006.01)
CPC G06F 21/602 (2013.01) [G06F 21/6218 (2013.01); G06F 21/71 (2013.01); G09C 1/00 (2013.01); H04L 9/0866 (2013.01); H04L 9/0877 (2013.01); H04L 9/30 (2013.01); H04L 9/3231 (2013.01); G06F 21/32 (2013.01); H04L 2209/125 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system on a chip (SoC), comprising:
one or more processors; and
a security circuit that includes a cryptographic accelerator circuit isolated from the one or more processors, wherein the cryptographic accelerator circuit is configured to:
perform a cryptographic operation responsive to a service request associated with the one or more processors, wherein performance of the cryptographic operation includes accessing key material stored in an internal memory of the cryptographic accelerator circuit; and
after performing of the cryptographic operation, zero the key material in the internal memory of the cryptographic accelerator circuit.