US 12,079,158 B2
Reconfigurable neural engine with extensible instruction set architecture
Sanket Pandit, San Jose, CA (US); Jorn Tuyls, Leinster (IE); Xiao Teng, Cupertino, CA (US); Rajeev Patwari, San Jose, CA (US); Ehsan Ghasemi, San Jose, CA (US); Elliott Delaye, San Jose, CA (US); and Aaron Ng, San Jose, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Jul. 25, 2022, as Appl. No. 17/814,817.
Prior Publication US 2024/0028556 A1, Jan. 25, 2024
Int. Cl. G06F 15/76 (2006.01); G06F 9/455 (2018.01); G06F 15/80 (2006.01)
CPC G06F 15/8053 (2013.01) [G06F 9/45533 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a plurality of kernels, wherein each kernel of the plurality of kernels is configured to perform a machine learning function;
a virtual machine coupled to the plurality of kernels;
wherein the plurality of kernels and the virtual machine run on hardware resources of the integrated circuit; and
wherein the virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels and control operation of the different ones of the plurality of kernels responsive to the instructions.