US 12,079,157 B2
Reconfigurable data processor with fast argument load using a runtime program on a host processor
Manish K. Shah, Austin, TX (US); and Gregory Frederick Grohoski, Bee Cave, TX (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Feb. 2, 2023, as Appl. No. 18/105,189.
Claims priority of provisional application 63/308,246, filed on Feb. 9, 2022.
Prior Publication US 2023/0305860 A1, Sep. 28, 2023
Int. Cl. G06F 15/78 (2006.01); G06F 9/30 (2018.01); G06F 9/445 (2018.01); G06F 15/80 (2006.01)
CPC G06F 15/80 (2013.01) [G06F 9/3013 (2013.01); G06F 9/44505 (2013.01); G06F 15/7867 (2013.01); G06F 15/7885 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A reconfigurable processor comprising:
an array of configurable units connected by a bus system, a configurable unit in the array of configurable units including a configuration data store, organized as a shift register, to store configuration data, the configuration data store also including individually addressable argument registers respectively comprising word-sized portions of the shift register adapted to provide arguments to the configurable unit, the configurable unit further including program load logic to receive sub-files of the configuration data via the bus system and to load the received sub-files into the configuration data store by sequentially shifting the received sub-files into the shift register, the configurable unit further including argument load logic to receive argument data via the bus system and load the received argument data into the argument registers without shifting the received argument data through the shift register;
a program load controller associated with the array to respond to a program load command by executing a program load process, including distributing a configuration file comprising the sub-files of configuration data to the configurable unit in the array as specified in the configuration file;
a fast argument load (FAL) controller associated with the array to respond to an FAL command by executing an FAL process, including distributing (value, control) tuples to the configurable unit as specified in an argument load file;
an interface unit in the array of configurable units, the interface unit coupled to the bus system;
an internal network coupled to the interface unit; and
an interface agent coupled between an external interface link and the internal network, to communicate data between the external interface link and the interface unit of the array of configurable units over the internal network, the interface agent configured to communicate with a host processor via the external interface link, and configurable to receive register read and register write requests from a runtime program running on the host processor that are addressed to memory-mapped registers in the interface unit of the array of configurable units and send the register read and register write requests over the internal network to the interface unit of the array of configurable units.