a plurality of multithreaded processor cores to execute instructions;

a plurality of input/output (IO) controllers coupled to the plurality of multithreaded processor cores, the plurality of IO controllers including one or more serial advanced technology attachment (SATA) controllers and one or more Peripheral Component Interconnect Express (PCIe) controllers;

a plurality of IO controller signal lines, respective ones of the plurality of IO controllers to communicate over a corresponding group of the IO controller signal lines in accordance with a corresponding IO protocol; and

a plurality of lanes, each lane of the plurality of lanes associated with a group of pins;

a lane mapping circuitry including a lane multiplexer to select from a plurality of communication paths between the plurality of lanes and the IO controller signal lines;

a power management controller to control power states associated with the plurality of multithreaded processor cores and the plurality of lanes;

a management controller to control the lane mapping circuitry during a transition of the apparatus from a powered off state to a powered state in accordance with default configuration information providing a default mapping of the plurality of IO controller signal lines or portions thereof to the plurality of lanes, the default configuration information read from a non-volatile memory,

wherein, based on the default mapping, the lane mapping circuitry is to couple sets of IO controller signal lines to sets of lanes of the plurality of lanes;

lane enablement circuitry configured to selectively enable and/or disable one or more lanes of the plurality of lanes.