US 12,079,147 B2
Memory device for efficiently determining whether to perform re-training operation and memory system including the same
Won-joo Jung, Bucheon-si (KR); Jang-woo Lee, Seoul (KR); Byung-hoon Jeong, Hwaseong-si (KR); and Jeong-don Ihm, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 17, 2023, as Appl. No. 18/170,949.
Application 18/170,949 is a continuation of application No. 16/999,168, filed on Aug. 21, 2020, granted, now 11,604,714.
Application 16/999,168 is a continuation in part of application No. 15/906,266, filed on Feb. 27, 2018, granted, now 10,754,563, issued on Aug. 25, 2020.
Claims priority of application No. 10-2017-0101352 (KR), filed on Aug. 9, 2017.
Prior Publication US 2023/0205711 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 1/10 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 12/0882 (2016.01); G06F 13/16 (2006.01); G06F 18/214 (2023.01)
CPC G06F 13/1673 (2013.01) [G06F 1/10 (2013.01); G06F 11/0757 (2013.01); G06F 11/3037 (2013.01); G06F 12/0882 (2013.01); G06F 18/2148 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a memory device, the method comprising:
receiving a write command from a memory controller;
receiving data including pattern data and write data from the memory controller through a signal transmission path;
generating check result information by performing a first operation of checking a state of the signal transmission path by using the pattern data;
performing a second operation of writing the write data to a page buffer circuit;
receiving a confirmation command from the memory controller; and
writing, in response to the confirmation command, the write data stored in the page buffer circuit to memory cells.