| CPC G06F 13/1642 (2013.01) [G06F 13/161 (2013.01); G06F 13/1668 (2013.01); G06F 13/374 (2013.01)] | 20 Claims |
|
1. An apparatus comprising:
a communication bus circuit including a command bus and a data bus separate from the command bus;
a memory circuit coupled to the communication bus circuit;
a queue manager circuit, coupled to the communication bus circuit, including a plurality of bus queues, and configured to:
receive a first memory request and a second memory request, each including a respective address value to be sent via the command bus, wherein the first, but not the second, memory request includes a corresponding data operand to be sent via the data bus; and
distribute the first memory request and the second memory request among the plurality of bus queues, wherein distribution of the first and second memory requests is based on the respective address values; and
an arbitration circuit configured to select, based on whether the data bus is available, a particular memory request from a particular one of the plurality of bus queues, wherein to select the particular memory request, the arbitration circuit is further configured to select the second memory request based at least on a determination that the data bus is not available.
|