US 12,079,142 B2
PC-based instruction group permissions
Jeffry E. Gonion, Campbell, CA (US); and Bernard J. Semeria, Palo Alto, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 28, 2023, as Appl. No. 18/343,145.
Claims priority of provisional application 63/356,074, filed on Jun. 28, 2022.
Prior Publication US 2023/0418929 A1, Dec. 28, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 12/1027 (2016.01); G06F 12/14 (2006.01); G06F 21/52 (2013.01)
CPC G06F 12/1483 (2013.01) [G06F 9/30076 (2013.01); G06F 9/30189 (2013.01); G06F 12/1027 (2013.01); G06F 12/1475 (2013.01); G06F 21/52 (2013.01); G06F 2221/034 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor that includes:
a permission table circuit configured to store a plurality of secondary execution privileges, wherein the permission table circuit is indexed by a particular secondary execution privileges index corresponding to a particular instruction to provide a particular secondary execution privileges value for the particular instruction that defines which of a plurality of instruction groups of an instruction set architecture (ISA) of the processor are executable from a first memory address at which the particular instruction is stored; and
a control circuit coupled to the permission table circuit and configured to selectively permit the processor to execute the particular instruction when the particular instruction is in a particular instruction group indicated by the particular secondary execution privileges value as being executable.