US 12,079,140 B2
Reducing translation lookaside buffer searches for splintered pages
John D. Pape, Cedar Park, TX (US); Brian R. Mestan, Austin, TX (US); and Peter G. Soderquist, Milford, MA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 24, 2023, as Appl. No. 18/189,982.
Application 18/189,982 is a continuation of application No. 17/016,229, filed on Sep. 9, 2020, granted, now 11,615,033, issued on Mar. 28, 2023.
Prior Publication US 2023/0236988 A1, Jul. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1027 (2016.01); G06F 9/455 (2018.01)
CPC G06F 12/1027 (2013.01) [G06F 9/45558 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more status registers implementing a plurality of splintered sticky bits for respective entries of a plurality of entries of a translation lookaside buffer (TLB); and
circuitry configured to:
receive a TLB invalidate corresponding to
a first entry of the plurality of entries of the TLB;
perform an index walk through all indices of the TLB responsive to a splintered sticky bit of the plurality of splintered sticky bits for the first entry having a first value; and
skip the index walk responsive to the splintered sticky bit having a second value different from the first value.