US 12,079,137 B2
Banked memory architecture for multiple parallel datapath channels in an accelerator
Stephen Sangho Youn, Bellevue, WA (US); Steven Karl Reinhardt, Vancouver, WA (US); and Hui Geng, Bellevue, WA (US)
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on May 30, 2023, as Appl. No. 18/203,527.
Application 18/203,527 is a continuation of application No. 17/730,707, filed on Apr. 27, 2022, granted, now 11,704,251.
Application 17/730,707 is a continuation of application No. 17/097,205, filed on Nov. 13, 2020, granted, now 11,347,652, issued on May 31, 2022.
Claims priority of provisional application 63/072,427, filed on Aug. 31, 2020.
Prior Publication US 2023/0305967 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0897 (2016.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01)
CPC G06F 12/0897 (2013.01) [G11C 7/1006 (2013.01); G11C 7/1057 (2013.01); G11C 7/1072 (2013.01); G11C 11/4076 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory architecture, comprising:
a plurality of memory banks, wherein each memory bank of the plurality of memory banks includes a vector register file (VRF);
a plurality of data channels, wherein each data channel of the plurality of data channels is paired with a separate memory bank of the plurality of memory banks and each data channel of the plurality of data channels includes a matrix-vector multiplier (MVM);
a deserializer that distributes an incoming data stream across the plurality of memory banks; and
a serializer that collects output data from the plurality of memory banks into a single data stream.