| CPC G06F 12/0891 (2013.01) | 20 Claims |
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1. A memory device comprising:
a set of memory cells;
a cache storage operatively coupled to the set of memory cells, the cache storage comprising a first data cache, a second data cache, and a third data cache;
an input/output (I/O) data cache operatively coupled to the cache storage and a host system; and
control logic, operatively coupled with the set of memory cells and the cache storage, to perform operations comprising:
executing a first programming operation to program the set of memory cells to a set of programming levels;
generating a first cache ready signal indicating to the host system to send first data associated with a second programming operation to the I/O data cache;
generating a first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells;
generating a second cache ready signal indicating to the host system to send second data associated with the second programming operation to the I/O data cache;
causing the first data associated with the second programming operation to be stored in the third data cache of the cache storage; and
generating a third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.
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