US 12,079,131 B2
Memory system and operating method thereof
Jooyoung Lee, Seoul (KR); and Hoeseung Jung, Seoul (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 12, 2022, as Appl. No. 17/743,014.
Application 17/743,014 is a continuation of application No. 16/909,719, filed on Jun. 23, 2020, granted, now 11,334,493.
Claims priority of application No. 10-2019-0137814 (KR), filed on Oct. 31, 2019.
Prior Publication US 2022/0269613 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0882 (2016.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 12/02 (2006.01); G06F 12/0846 (2016.01)
CPC G06F 12/0882 (2013.01) [G06F 9/5016 (2013.01); G06F 9/505 (2013.01); G06F 9/544 (2013.01); G06F 12/0246 (2013.01); G06F 12/0851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory device including a plurality of memory blocks; and
a controller suitable for dynamically changing a size of a write buffer based on whether a current workload is a sequential workload or a mixed workload in which read commands are provided between write commands together with the write commands,
wherein the controller comprises:
a workload detecting unit suitable for increasing a write count for the write commands when a write command is received, increasing a read count for the read commands when a read command is received, and initiating the write count when the read command is received.