US 12,079,126 B2
Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction
John G. Favor, San Francisco, CA (US); and Srivatsan Srinivasan, Cedar Park, TX (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on May 18, 2022, as Appl. No. 17/747,703.
Application 17/747,703 is a continuation in part of application No. 17/370,009, filed on Jul. 8, 2021, granted, now 11,481,332.
Application 17/747,703 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/747,703 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/370,009 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/370,009 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/351,927 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/370,009 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/747,703 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Claims priority of provisional application 63/331,487, filed on Apr. 15, 2022.
Claims priority of provisional application 63/271,934, filed on Oct. 26, 2021.
Prior Publication US 2022/0358040 A1, Nov. 10, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 12/0815 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 9/30043 (2013.01); G06F 9/5016 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A microprocessor, comprising:
a cache memory;
a store queue, wherein each entry of the store queue is configured to hold store data associated with a store instruction; and
a load/store unit configured to, during execution of a load instruction:
make a determination that an entry of the store queue holds store data that includes some but not all bytes of load data requested by the load instruction;
cancel execution of the load instruction in response to the determination; and
write to an entry of a structure from which the load instruction is subsequently issuable for re-execution:
an identifier of a store instruction that is older in program order than the load instruction; and
an indication that the load instruction is not eligible to re-execute until the identified older store instruction updates the cache memory with store data.