US 12,079,098 B2
Automated test equipment with hardware accelerator
Mei-Mei Su, San Jose, CA (US); Eddy Wayne Chow, San Jose, CA (US); and Edmundo De La Puente, San Jose, CA (US)
Assigned to Advantest Corporation, Tokyo (JP)
Filed by Advantest Corporation, Tokyo (JP)
Filed on Dec. 28, 2020, as Appl. No. 17/135,790.
Application 17/135,790 is a continuation in part of application No. 15/914,553, filed on Mar. 7, 2018, granted, now 11,009,550.
Application 15/914,553 is a continuation in part of application No. 13/773,569, filed on Feb. 21, 2013, granted, now 10,162,007, issued on Dec. 25, 2018.
Claims priority of provisional application 62/988,612, filed on Mar. 12, 2020.
Prior Publication US 2021/0117298 A1, Apr. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/273 (2006.01); G01R 31/317 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/2736 (2013.01) [G01R 31/31724 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0028 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An automated test equipment (ATE) system comprising:
a system controller communicatively coupled to a tester processor, wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs); and
an FPGA communicatively coupled to the tester processor, wherein the FPGA comprises a hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the plurality of DUTs, wherein the tester processor is configured to operate in one of a plurality of functional modes, the plurality of functional modes configured to allocate functionality for generating commands and data between the tester processor and the FPGA.