US 12,079,097 B2
Techniques for testing semiconductor devices
Animesh Khare, Bangladore (IN); Ashish Kumar, Patna (IN); Shantanu Sarangi, Saratoga, CA (US); and Rahul Garg, Jind (IN)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Oct. 20, 2020, as Appl. No. 17/075,628.
Prior Publication US 2022/0121542 A1, Apr. 21, 2022
Int. Cl. G06F 11/273 (2006.01); G06F 11/22 (2006.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/2733 (2013.01) [G06F 11/2268 (2013.01); G06F 13/28 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
7. A semiconductor device, comprising:
a plurality of components;
a test bus; and
a test data transfer unit;
wherein the test data transfer unit:
receives, from a host computer, configuration information for performing a test of the semiconductor device;
reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, wherein the memory of the host computer that stores the test data read by the semiconductor device is external to the semiconductor device;
sends the test data to the plurality of components via the test bus;
causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test; and
after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.