US 12,079,080 B2
Memory controller performing selective and parallel error correction, system including the same and operating method of memory device
Hyeokjun Choe, Hwaseong-si (KR); Heehyun Nam, Seoul (KR); Jeongho Lee, Gwacheon-si (KR); and Younho Jeon, Gimhae-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 15, 2023, as Appl. No. 18/335,375.
Application 18/335,375 is a continuation of application No. 17/510,898, filed on Oct. 26, 2021, granted, now 11,720,442.
Claims priority of application No. 10-2020-0154848 (KR), filed on Nov. 18, 2020.
Prior Publication US 2023/0325277 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/15 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/0772 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by a Compute Express Link™ (CXL) device connected to a host processor, the CXL device supporting a CXL memory protocol and at least one second protocol selected from a coherent protocol and a non-coherent protocol, the method comprising:
receiving a first read request from the host processor based on the CXL memory protocol;
transmitting the first read request to a device-attached memory and reading first read data corresponding to the first read request from the memory based on the second protocol;
detecting an error of the first read data;
correcting the error included in the first read data based on at least one of a reference latency or a reference error correction level included in a first error correction option; and
providing first correction data to the host processor based on the CXL memory protocol.