US 12,079,078 B2
Command address fault detection
Melissa I. Uribe, El Dorado Hills, CA (US); and Steffen Buch, Taufkirchen (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 16, 2022, as Appl. No. 17/820,120.
Prior Publication US 2024/0061744 A1, Feb. 22, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 11/079 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
receive, from a host device via a command address (CA) bus, a plurality of CA bits conveyed by a command signal or an address signal;
receive, from the host device via the CA bus, a first set of parity bits,
wherein the first set of parity bits is generated based on applying a select parity generation process to the plurality of CA bits conveyed by the command signal or the address signal;
generate a second set of parity bits, based on applying the select parity generation process to the plurality of CA bits conveyed by the command signal or the address signal;
compare the first set of parity bits and the second set of parity bits; and
determine whether to transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.