US 12,079,077 B2
Device fault condition reporting
Crescenzo Attanasio, Acerra (IT); Carminantonio Manganelli, San Giorgio del Sannio (IT); Massimo Iaculo, San Marco Evangelista (IT); Paolo Papa, Naples (IT); and Antonio Eliso, Boscoreale (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2021, as Appl. No. 17/645,180.
Claims priority of provisional application 63/140,378, filed on Jan. 22, 2021.
Prior Publication US 2022/0237080 A1, Jul. 28, 2022
Int. Cl. G06F 11/00 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 11/0757 (2013.01); G06F 11/0772 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device comprising one or more arrays of memory; and
a control circuit coupled with the memory device and configured to cause the apparatus to:
receive, from a host system, a command to perform an operation on the one or more arrays of memory of the memory device;
deallocate buffer resources associated with data from the host system;
receive a notification based at least in part on deallocating the buffer resources;
identify, by the memory device, a fault condition of the memory device associated with performing the operation in response to receiving the command and based at least in part on receiving the notification;
transmit, from the memory device to the host system, a message that indicates the fault condition based at least in part on identifying the fault condition, wherein the message comprises an indication of the command; and
enter a safe mode of operation based at least in part on identifying the fault condition.