US 12,079,076 B2
Apparatuses, systems, and methods for error correction
Yoshinori Fujiwara, Boise, ID (US); Vivek Kotti, Boise, ID (US); Christopher G. Wieduwilt, Boise, ID (US); Jason M. Johnson, Nampa, ID (US); and Kevin G. Werhane, Nampa, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Feb. 2, 2022, as Appl. No. 17/591,362.
Application 17/591,362 is a continuation of application No. 16/748,554, filed on Jan. 21, 2020, granted, now 11,263,078.
Claims priority of provisional application 62/955,869, filed on Dec. 31, 2019.
Prior Publication US 2022/0156148 A1, May 19, 2022
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1032 (2013.01); G06F 11/1044 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method comprising:
activating a word line of a memory as part of a read operation;
activating a first portion of the word line on a first side of a row decoder and a second portion of the word line on a second side of the row decoder as part of the same read operation, wherein the first side is opposite the second side;
receiving, with a first error correction code (ECC) circuit, a first set of data and a first set of parity bits in parallel from a first set of memory cells of the word line, wherein the first set of memory cells are non-adjacent to each other;
receiving, with a second error correction code (ECC) circuit, a second set of data and a second set of parity bits in parallel from a second set of memory cells of the word line, wherein the second set of memory cells are non-adjacent to each other;
correcting the first set of data based on the first set of parity bits with the first BCC circuit and correcting the second set of data based on the second set of parity bits with the second ECC circuit; and
providing the corrected first set of data from the first ECC circuit and the corrected second set of data from the second ECC circuit to an input/output circuit which is coupled to a plurality of data terminals.