US 12,079,075 B2
Semiconductor storage apparatus and ECC related information reading method
Takehiro Kaminaga, Kanagawa (JP)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Apr. 22, 2021, as Appl. No. 17/238,158.
Claims priority of application No. 2020-084259 (JP), filed on May 13, 2020.
Prior Publication US 2021/0357288 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G06F 11/1068 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor storage apparatus, comprising:
a NAND memory cell array;
a continuous reading component, continuously reading a predetermined number of pages of the NAND memory cell array in sequential in units of pages, the continuous reading component comprises a first latch and a second latch, the first latch and the second latch are connected in series and sequentially holds page data of each of the predetermined number of pages during continuous reading of the predetermined number of pages, wherein both of the first latch and the second latch include a first cache and a second cache, during continuous reading of the predetermined number of pages, the page data read from the NAND memory cell array is transmitted to the first latch, ½ page data read from the NAND memory cell array is held in the first cache of the first latch, the other ½ page data read from the NAND memory cell array is held in the second cache of the first latch, and the page data held in the first latch is transmitted to the first cache or the second cache of the second latch in units of ½ page, the ½ page data held in the first cache of the first latch is transmitted to the first cache of the second latch, the other ½ page data held in the second cache of the first latch is transmitted to the second cache of the second latch, during a period of outputting the page data held in the second latch to outside of the semiconductor storage apparatus, the page data of a next page is transmitted to the first latch;
an ECC circuit, coupled to the continuous reading component, performing ECC processing to the page data of each of the predetermined number of pages held in the first cache and the second cache of the second latch before the period of outputting the page data held in the second latch to outside of the semiconductor storage apparatus;
a memory component;
an output component; and
a controller, coupled to the continuous reading component, the ECC circuit, the memory component and the output component, monitoring a part of the pages whose page data has been error-corrected by the ECC circuit and storing ECC related information, only related to the part of the pages whose page data has been error-corrected by the ECC circuit, in the memory component during continuous reading of the predetermined number of pages,
wherein, the controller outputting the ECC related information, stored in the memory component, to a host apparatus through the output component in response to a read command after the continuous reading operation.