a memory array comprising an array of memory cells that each comprise capacitive storage elements;

a circuit coupled with the memory array and configured to cause the apparatus to:

transmit, to a host device, a first signal comprising a set of error control bits indicating that an error log of the apparatus comprises information for use by the host device;

receive, from the host device in response to the first signal, a second signal comprising a request to retrieve the information of the error log; and

transmit, to the host device in response to the second signal, a third signal comprising the information of the error log.