US 12,079,065 B2
Caching lookup tables for block family error avoidance
Shakeel Isamohiuddin Bukhari, San Jose, CA (US); and Mark Ish, Manassas, VA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 14, 2022, as Appl. No. 17/931,937.
Claims priority of provisional application 63/374,140, filed on Aug. 31, 2022.
Prior Publication US 2024/0069997 A1, Feb. 29, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 12/02 (2006.01); G06F 12/12 (2016.01)
CPC G06F 11/004 (2013.01) [G06F 12/0215 (2013.01); G06F 12/12 (2013.01); G06F 2212/251 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
determine a subset of one or more block family error avoidance (BFEA) lookup tables associated with a first memory location of the memory device, wherein the one or more BFEA lookup tables are stored in a second memory location of the memory device that is different from the first memory location;
cache the subset of the one or more BFEA lookup tables in the first memory location;
receive a read command associated with host data associated with the first memory location, wherein the host data is associated with a block family;
determine, based on the block family and the subset of the one or more BFEA tables cached in the first memory location, a threshold voltage offset associated with the host data;
compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data; and
read, using the modified threshold voltage, the host data from the first memory location.