US 12,079,060 B2
Memory system
Akihiro Kimura, Aichi (JP); and Hiroki Matsushita, Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Nov. 21, 2022, as Appl. No. 17/991,718.
Application 17/991,718 is a continuation of application No. 16/377,112, filed on Apr. 5, 2019, granted, now 11,507,173.
Application 16/377,112 is a continuation of application No. 15/984,259, filed on May 18, 2018, granted, now 10,254,817, issued on Apr. 9, 2019.
Application 15/984,259 is a continuation of application No. 15/489,253, filed on Apr. 17, 2017, granted, now 9,996,139, issued on Jun. 12, 2018.
Application 15/489,253 is a continuation of application No. 13/782,951, filed on Mar. 1, 2013, granted, now 9,652,377, issued on May 16, 2017.
Claims priority of application No. 2012-064253 (JP), filed on Mar. 21, 2012.
Prior Publication US 2023/0091553 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 1/3234 (2019.01); G06F 11/14 (2006.01); G06F 12/02 (2006.01); G11C 5/14 (2006.01)
CPC G06F 1/3275 (2013.01) [G06F 3/0619 (2013.01); G06F 11/1456 (2013.01); G06F 11/1458 (2013.01); G06F 12/0246 (2013.01); G11C 5/141 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7203 (2013.01); Y02D 10/00 (2018.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a first memory configured to store data in a volatile manner;
a second memory configured to store data in a nonvolatile manner;
a battery configured to be charged by a first power from outside of the memory system and generate a second power;
a power supply circuit configured to supply a third power based on either the first power or the second power depending on a voltage level of the first power; and
a control circuit configured to:
start an operation of saving data stored in the first memory to the second memory using the third power based on the first power, when the voltage level of the first power drops to a first value, and
continue the operation of saving the data stored in the first memory to the second memory using the third power based on the second power, when the voltage level of the first power drops further to a second value that is lower than the first value.