US 12,079,018 B2
Voltage regulator
Masayuki Usuda, Ota Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 12, 2023, as Appl. No. 18/332,756.
Application 15/466,347 is a division of application No. 14/838,069, filed on Aug. 27, 2015, granted, now 9,645,592, issued on May 9, 2017.
Application 14/838,069 is a division of application No. 14/015,990, filed on Aug. 30, 2013, granted, now 9,141,120, issued on Sep. 22, 2015.
Application 18/332,756 is a continuation of application No. 17/893,772, filed on Aug. 23, 2022, granted, now 11,675,377.
Application 17/893,772 is a continuation of application No. 17/209,108, filed on Mar. 22, 2021, granted, now 11,429,126, issued on Aug. 30, 2022.
Application 17/209,108 is a continuation of application No. 16/786,030, filed on Feb. 10, 2020, granted, now 10,955,866, issued on Mar. 23, 2021.
Application 16/786,030 is a continuation of application No. 16/271,666, filed on Feb. 8, 2019, granted, now 10,558,231, issued on Feb. 11, 2020.
Application 16/271,666 is a continuation of application No. 15/888,438, filed on Feb. 5, 2018, granted, now 10,209,724, issued on Feb. 19, 2019.
Application 15/888,438 is a continuation of application No. 15/466,347, filed on Mar. 22, 2017, granted, now 9,886,046, issued on Feb. 6, 2018.
Claims priority of application No. 2012-241904 (JP), filed on Nov. 1, 2012.
Prior Publication US 2023/0324939 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G05F 1/569 (2006.01); G05F 1/575 (2006.01)
CPC G05F 1/569 (2013.01) [G05F 1/575 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit; and
a voltage regulator connected to the first circuit and including:
a first terminal;
a second terminal;
a third terminal;
a second circuit between the first and second terminals, including a first transistor, and configured to operate based on first and second voltages both provided to the second circuit;
a second transistor between the first and third terminals; and
a third circuit including a third transistor and configured to control on and off of the second transistor based on current flowing through the third transistor, wherein
the current flowing through the third transistor corresponds to current flowing through the first transistor, and
the current flowing through the first transistor varies based on a difference between the first and second voltages, the second voltage being proportional to a third voltage of the third terminal.