a control register that holds one of a plurality of pixel modes as a setting value;

a pixel array that includes an arrangement of a plurality of light receiving elements each detecting incidence of photons;

a reading circuit that reads detection signal from each of the light receiving elements with a sampling period;

a pixel value generating circuit that tallies, in units of pixels, number of the detection signal read from each of the plurality of light receiving elements with the sampling period, and generates, for each of the sampling period, pixel value of each pixel; and

a memory that is configured to store, for each of the pixels, a histogram of the pixel values in each of the sampling period as calculated by the pixel value generating circuit, wherein

each pixel is made of one or more light receiving elements from among the plurality of light receiving elements,

when a first pixel mode is held in the control register, an area having a first size in the memory is allotted to each pixel, and

when a second pixel mode is held in the control register, an area having a second size in the memory, which is different than the first size, is allotted to each pixel, and

wherein the pixel value generating circuit includes

an adding circuit that tallies, for a number of the light receiving elements equal to a first predetermined count, a number of the detection signal output from each of the plurality light receiving elements, and outputs a first-type pixel value, and

a variable-parallel adding circuit that outputs the pixel value of each pixel based on the first-type pixel value output from the adding circuit,

when the first pixel mode is held in the control register, the variable-parallel adding circuit outputs the first-type pixel value as the pixel value of each pixel, and

when the second pixel mode is held in the control register, the variable-parallel adding circuit outputs a value obtained by adding at least two of the first-type pixel values as the pixel value of each pixel.