a clock generator;

a master latch having a scan path and a data path independent of each other; and

a slave latch,

wherein the scan path performs an operation on an inverted scan enable signal and an inverted scan input signal and outputs a scan path signal according to an output signal of the clock generator, and

the data path includes:

a NAND circuit performing a NAND operation on a clock signal and a first latch signal and outputting a modified clock signal; and

an AOI circuit receiving the inverted scan enable signal, the modified clock signal, and a data signal, performing an AND operation on the inverted scan enable signal, the modified clock signal, and the data signal, performing a NOR operation on the scan path signal and a signal obtained by the AND operation, and outputting a signal obtained by the NOR operation as a first latch signal of the next stage.