US 12,408,568 B2
RRAM device structure and manufacturing method
Chung-Liang Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 1, 2023, as Appl. No. 18/310,361.
Application 18/310,361 is a continuation of application No. 17/193,843, filed on Mar. 5, 2021, granted, now 11,653,581.
Claims priority of provisional application 63/065,367, filed on Aug. 13, 2020.
Prior Publication US 2023/0270022 A1, Aug. 24, 2023
Int. Cl. H10N 70/00 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01)
CPC H10N 70/841 (2023.02) [H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/061 (2023.02); H10N 70/826 (2023.02); G11C 13/003 (2013.01); G11C 2213/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a resistive random access memory cell including:
a resistor device including:
a first electrode including a plurality of conductive nanosheets;
a resistive element at least partially surrounding the conductive nanosheets; and
a second electrode separated from the conductive nanosheets by the resistive element.