US 12,408,557 B2
Methods for forming structures with desired crystallinity for MRAM applications
Lin Xue, San Diego, CA (US); Jaesoo Ahn, Fremont, CA (US); Mahendra Pakala, Santa Clara, CA (US); Chi Hong Ching, Santa Clara, CA (US); and Rongjun Wang, Dublin, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Sep. 27, 2021, as Appl. No. 17/486,649.
Application 17/486,649 is a division of application No. 15/438,420, filed on Feb. 21, 2017, granted, now 11,133,460.
Application 15/438,420 is a division of application No. 15/199,006, filed on Jun. 30, 2016, granted, now 11,245,069.
Claims priority of provisional application 62/192,565, filed on Jul. 14, 2015.
Prior Publication US 2022/0013716 A1, Jan. 13, 2022
Int. Cl. H10N 50/01 (2023.01); H01F 10/14 (2006.01); H01F 10/32 (2006.01); H10N 50/10 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/01 (2023.02) [H01F 10/14 (2013.01); H01F 10/3222 (2013.01); H10N 50/10 (2023.02); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a magnetic tunnel junction structure on a substrate, comprising:
patterning a film stack having a tunneling barrier layer disposed between a magnetic reference layer and a magnetic storage layer disposed on a substrate to remove a portion of the film stack from the substrate until an upper surface of the substrate is exposed, wherein the magnetic storage layer comprises a first magnetic storage sublayer, a second magnetic storage sublayer and a metallic intermediate layer therebetween;
forming a conformal sidewall passivation layer on sidewalls of the patterned film stack, wherein the sidewall passivation layer is in direct contact with a top surface of the substrate and covering the top surface, wherein the sidewall passivation layer has a vertical portion continuously coplanar along a vertical axis normal to a major axis of the substrate and a horizontal portion in direct contact with the substrate and extending outwardly from the vertical portion along the substrate;
forming an insulation layer comprising silicon oxide, where the portion of the film stack was removed during patterning, that is in direct contact with the sidewall passivation layer such that the horizontal portion is between the insulation layer and the substrate and the insulation layer does not contact the top surface of the substrate; and
subsequently performing a thermal annealing process to the film stack, wherein the insulation layer extends from a top surface of the sidewall passivation layer to the horizontal portion of the sidewall passivation layer
wherein the film stack further comprises a pinning layer disposed between the substrate and the magnetic reference layer, the pinning layer further comprising sequentially from the magnetic reference layer in the direction of the substrate; a Co layer, a Co/Pt layer, an Ru layer, a Co layer, a Co/Pt layer, a Pt layer, a Ta layer, an Ru layer, a Ta layer, and a TaN layer.