US 12,408,522 B2
Display substrate and method for manufacturing the same, and display apparatus
Yang Zhou, Beijing (CN); Yao Huang, Beijing (CN); Shun Zhang, Beijing (CN); Huijuan Yang, Beijing (CN); Yupeng He, Beijing (CN); Xin Zhang, Beijing (CN); Yu Wang, Beijing (CN); Tinghua Shang, Beijing (CN); and Yiyang Zhang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/619,603
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Mar. 15, 2021, PCT No. PCT/CN2021/080875
§ 371(c)(1), (2) Date Dec. 16, 2021,
PCT Pub. No. WO2021/203917, PCT Pub. Date Oct. 14, 2021.
Prior Publication US 2023/0157096 A1, May 18, 2023
Int. Cl. H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 59/65 (2023.01); H10K 59/80 (2023.01); H10K 59/88 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/1201 (2023.02); H10K 59/873 (2023.02); H10K 59/88 (2023.02); H10K 59/65 (2023.02); H10K 59/8731 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A display substrate having a display area, the display area having an enclosed area, the enclosed area including a hole border area, at least two wiring areas, at least one through hole area, and at least one blind hole area, the blind hole area being light-transmitting; a blind hole being provided in each blind hole area, each through hole area and each blind hole area being both surrounded by a respective wiring area of the at least two wiring areas, the hole border area surrounding the wiring areas, and the display area surrounding the hole border area, the display substrate comprising:
a base substrate, the base substrate having a through hole in each through hole area; and
a driving circuit layer disposed on the base substrate, wherein the driving circuit layer includes:
at least one metal layer located in the display area, the hole border area and the wiring areas, the at least one metal layer including a plurality of signal lines, a first gate layer, a second gate layer, and a source-drain metal layer, and the plurality of signal lines being disposed to avoid the at least one through hole area and the at least one blind hole area;
at least one insulating layer located in the display area, the hole border area, the wiring areas and the at least one blind hole area, the at least one insulating layer includes a first insulating layer, a second insulating layer, and an interlayer insulating layer; and
a semiconductor layer located in the display area and the hole border area, wherein
the semiconductor layer is disposed on a side of the base substrate;
the first insulating layer is disposed on a side of the semiconductor layer away from the base substrate;
the first gate layer is disposed on a side of the first insulating layer away from the base substrate;
the second insulating layer is disposed on a side of the first gate layer away from the base substrate;
the second gate layer is disposed on a side of the second insulating layer away from the base substrate;
the interlayer insulating layer is disposed on a side of the second gate layer away from the base substrate; and
the source-drain metal layer is disposed on a side of the interlayer insulating layer away from the base substrate;
wherein the display substrate further has at least one encapsulation dam area, each encapsulation dam area being located between a through hole area of the at least one through hole area and the wiring area of the at least two wiring areas surrounding the through hole area, and surrounding the through hole area of the at least one through hole area, wherein the first insulating layer, the second insulating layer, and the interlayer insulating layer are further located in the at least one encapsulation dam area; and
the display substrate further comprises:
one or more encapsulation dams, wherein each encapsulation dam area is provided with at least one encapsulation dam therein, the encapsulation dam surrounds the through hole area of the at least one through hole area, and the encapsulation dam is disposed on a side of the driving circuit layer away from the base substrate, wherein
the at least one encapsulation dam includes one encapsulation dam; or
the at least one encapsulation dam includes at least two encapsulation dams, the at least two encapsulation dams are disposed along a radial direction of the through hole area of the at least one through hole area at intervals in sequence.