US 12,408,486 B2
High efficiency microdevice
Gholamreza Chaji, Waterloo (CA); Ehsanollah Fathi, Waterloo (CA); and Hossein Zamani Siboni, Waterloo (CA)
Assigned to VueReal Inc., Waterloo (CA)
Appl. No. 17/631,005
Filed by VueReal Inc., Waterloo (CA)
PCT Filed Jul. 29, 2020, PCT No. PCT/CA2020/051042
§ 371(c)(1), (2) Date Jan. 28, 2022,
PCT Pub. No. WO2021/016712, PCT Pub. Date Feb. 4, 2021.
Claims priority of provisional application 62/964,184, filed on Jan. 22, 2020.
Claims priority of provisional application 62/880,498, filed on Jul. 30, 2019.
Prior Publication US 2022/0302338 A1, Sep. 22, 2022
Int. Cl. H10H 20/816 (2025.01); H01L 23/58 (2006.01); H10H 20/00 (2025.01); H10H 20/811 (2025.01); H10H 20/812 (2025.01)
CPC H10H 20/816 (2025.01) [H01L 23/58 (2013.01); H10H 20/062 (2025.01); H10H 20/811 (2025.01); H10H 20/812 (2025.01); H10H 20/8162 (2025.01); H10H 20/052 (2025.01)] 5 Claims
OG exemplary drawing
 
1. A method to increase efficiency in a vertical solid state device, the method comprising:
providing a solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure;
applying a biasing voltage to a gate electrode connected to the MIS structure and shorting the MIS structure to a n-contact of the vertical solid state device; and
keeping the biasing voltage of the gate electrode less than a threshold voltage of the MIS structure to increase the efficiency of the vertical solid state device.