US 12,408,466 B2
High-speed readout image sensor
Chi-Hsien Chung, New Taipei (TW); Tzu-Jui Wang, Fengshan (TW); Shang-Fu Yeh, Hsin Chu (TW); Tzu-Hsuan Hsu, Kaohsiung (TW); Chen-Jong Wang, Hsin-Chu (TW); and Dun-Nian Yaung, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 4, 2023, as Appl. No. 18/149,746.
Claims priority of provisional application 63/431,059, filed on Dec. 8, 2022.
Claims priority of provisional application 63/359,981, filed on Jul. 11, 2022.
Prior Publication US 2024/0014245 A1, Jan. 11, 2024
Int. Cl. H10F 39/00 (2025.01)
CPC H10F 39/811 (2025.01) [H10F 39/809 (2025.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An image sensor comprising:
a first chip comprising:
a first semiconductor substrate, wherein the first semiconductor substrate has a first side and a second side, and wherein the second side of the first semiconductor substrate is opposite the first side of the first semiconductor substrate;
a first transistor cell and a second transistor cell disposed in a transistor cell array, wherein the first transistor cell comprises a first plurality of transistors disposed along the first side of the first semiconductor substrate, wherein the first transistor cell is configured to operate a first photodetector cell, wherein the second transistor cell comprises a second plurality of transistors disposed along the first side of the first semiconductor substrate, wherein the second transistor cell is configured to operate a second photodetector cell, and wherein the second transistor cell is laterally spaced from the first transistor cell;
a first through-substrate via (TSV) extending vertically through the first semiconductor substrate, wherein the first transistor cell is electrically coupled to the first TSV, wherein the first transistor cell is configured to provide a first signal to the first TSV that corresponds to a number of charges accumulated in a photodetector of the first photodetector cell; and
a second TSV extending vertically through the first semiconductor substrate, wherein the second transistor cell is electrically coupled to the second TSV, wherein the second transistor cell is configured to provide a second signal to the second TSV that corresponds to a number of charges accumulated in a photodetector of the second photodetector cell;
a second chip comprising:
a second semiconductor substrate, wherein the second chip is bonded to the first chip;
a first interlayer dielectric (ILD) structure disposed vertically between the second semiconductor substrate and the first semiconductor substrate, and wherein the first side of the first semiconductor substrate is disposed vertically between the second side of the first semiconductor substrate and the second semiconductor substrate; and
a first readout circuit electrically coupled to the first TSV and to the second TSV, wherein the first readout circuit is disposed laterally, at least partially, between the first TSV and the second TSV.