US 12,408,461 B2
Semiconductor structure with isolation structure
Ching-Heng Liu, Miaoli County (TW); Chang Yu Kuo, Miaoli County (TW); and Ya-Wen Wu, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on Jun. 16, 2022, as Appl. No. 17/842,202.
Prior Publication US 2023/0411421 A1, Dec. 21, 2023
Int. Cl. H10F 39/00 (2025.01); H10D 84/80 (2025.01); H10F 39/18 (2025.01)
CPC H10F 39/807 (2025.01) [H10F 39/014 (2025.01); H10F 39/18 (2025.01); H10F 39/8067 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first shallow trench isolation (STI) structure within a semiconductor substrate, wherein:
the first STI structure comprises a buffer structure, an adhesion structure, an electromagnetic reflection structure, and a fill structure;
the adhesion structure is between and adhesively bonded to the buffer structure and the electromagnetic reflection structure;
the electromagnetic reflection structure is between the adhesion structure and the fill structure to reflect electromagnetic radiation;
the buffer structure comprises a first oxide layer formed within a shallow trench of the semiconductor substrate; and
the fill structure comprises a second oxide layer that covers a top surface of the adhesion structure, a top surface of the electromagnetic reflection structure, and an inner surface of the electromagnetic reflection structure.