| CPC H10D 89/10 (2025.01) [H01L 21/76224 (2013.01); H10D 30/6219 (2025.01); H10D 62/114 (2025.01); H10D 62/115 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/0172 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 84/856 (2025.01); H10D 84/859 (2025.01); H01L 21/31053 (2013.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 62/834 (2025.01); H10D 64/62 (2025.01); H10D 64/665 (2025.01); H10D 64/667 (2025.01); H10D 64/691 (2025.01); H10D 84/0188 (2025.01)] | 20 Claims |

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1. A semiconductor structure, comprising:
a first device comprising:
a first plurality of fins extending in parallel along a first direction and comprising a first channel region and a first source/drain region,
a first gate structure wrapping over each of the first plurality of fins, and
a first source/drain contact disposed over the first source/drain region; and
a second device comprising:
a first fin extending lengthwise along the first direction and aligned with one of the first plurality of fins along the first direction, the first fin comprising a second channel region and a second source/drain region,
a second gate structure wrapping over the first fin, and
a second source/drain contact disposed over the second source/drain region,
wherein the first source/drain contact comprises a first length along a second direction perpendicular to the first direction,
wherein the second source/drain contact comprises a second length along the second direction, and
wherein a ratio of the first length to the second length is between about 1.1 and about 2.0.
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