| CPC H10D 86/411 (2025.01) [G09G 3/3233 (2013.01); H10K 71/00 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); H10K 59/1201 (2023.02); H10K 59/131 (2023.02)] | 18 Claims |
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1. A display substrate, comprising:
a display region, a notch region, and a capacitance compensation region, wherein the display region at least partially surrounds the notch region, and the capacitance compensation region is located between the display region and the notch region; a plurality of first gate lines is provided in the display region;
a first capacitance compensation unit is provided in the capacitance compensation region;
the first capacitance compensation unit comprises a semiconductor structure, a first metal structure, and a second metal structure disposed on a base substrate sequentially; the semiconductor structure and the first metal structure are insulated from each other, and the first metal structure and the second metal structure are insulated from each other; a plurality of first vias are provided in an insulation layer between the semiconductor structure and the second metal structure, and the second metal structure is connected with the semiconductor structure through the plurality of first vias;
the first metal structure comprises a plurality of second gate lines extending along a first direction, and at least one of the second gate lines is connected with a corresponding first gate line; an orthographic projection of a second gate line on the base substrate is at least partially overlapped with an orthographic projection of the second metal structure on the base substrate, and the orthographic projection of the second gate line on the base substrate is at least partially overlapped with an orthographic projection of the semiconductor structure on the base substrate; the second gate line forms a capacitor together with the second metal structure and the semiconductor structure; and
the plurality of first vias are arranged along the first direction, and in a second direction perpendicular to the first direction, a distance between two adjacent first vias is at least greater than a sum of widths of two second gate lines,
wherein the second metal structure at least comprises a first potential signal line extending along the first direction, and
wherein the first potential signal line in the capacitance compensation region has a main body portion and an extension portion; the main body portion extends along the first direction, the extension portion extends along the second direction, and one end of the extension portion close to the notch region is connected with the main body portion; a length of the extension portion in the first direction increases gradually and then decreases along a direction away from the notch region.
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17. A preparation method of a display substrate, wherein the display substrate comprises a display region, a notch region, and a capacitance compensation region, the display region at least partially surrounds the notch region, and the capacitance compensation region is located between the display region and the notch region;
the preparation method comprises:
providing a base substrate; and
in the capacitance compensation region, forming a semiconductor structure, a first metal structure, and a second metal structure on the base substrate sequentially; wherein the semiconductor structure and the first metal structure are insulated from each other, the first metal structure and the second metal structure are insulated from each other, a plurality of first vias are provided in an insulation layer between the semiconductor structure and the second metal structure, and the second metal structure is connected with the semiconductor structure through the plurality of first vias; the first metal structure comprises a plurality of second gate lines extending along a first direction, and the second gate lines are respectively connected with a plurality of first gate lines in the display region; an orthographic projection of a second gate line on the base substrate is at least partially overlapped with an orthographic projection of the second metal structure on the base substrate, and the orthographic projection of the second gate line on the base substrate is at least partially overlapped with an orthographic projection of the semiconductor structure on the base substrate; the second gate line forms a capacitor together with the second metal structure and the semiconductor structure; the plurality of first vias are arranged along the first direction, and in a second direction perpendicular to the first direction, a distance between two adjacent first vias is at least greater than a sum of widths of two second gate lines,
wherein the second metal structure at least comprises a first potential signal line extending along the first direction, and
wherein the first potential signal line in the capacitance compensation region has a main body portion and an extension portion; the main body portion extends along the first direction, the extension portion extends along the second direction, and one end of the extension portion close to the notch region is connected with the main body portion; a length of the extension portion in the first direction increases gradually and then decreases along a direction away from the notch region.
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