US 12,408,431 B2
Gate stack quality for gate-all-around field-effect transistors
Jingyun Zhang, Albany, NY (US); Takashi Ando, Tuckahoe, NY (US); and Choonghyun Lee, Rensselaer, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Oct. 24, 2019, as Appl. No. 16/662,865.
Application 16/662,865 is a division of application No. 15/947,411, filed on Apr. 6, 2018, granted, now 10,566,435, issued on Feb. 18, 2020.
Prior Publication US 2021/0126018 A1, Apr. 29, 2021
Int. Cl. H01L 27/12 (2006.01); H10D 30/67 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 86/00 (2025.01)
CPC H10D 86/215 (2025.01) [H10D 30/6735 (2025.01); H10D 64/516 (2025.01); H10D 84/0144 (2025.01); H10D 84/038 (2025.01); H10D 30/6736 (2025.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first gate-all-around field-effect transistor (GAA FET) device including a first vertical gate stack having a plurality of first channels, first interfacial layers formed around the first channels, and a number of first dielectric material layers including a high-k dielectric formed around the first interfacial layers, the first GAA FET including a first threshold voltage;
a second GAA FET device including a second vertical gate stack having a plurality of second channels, second interfacial layers formed around and in contact with the second channels, second gate dielectric material layers formed around and in contact with the second interfacial layers including a same number of dielectric material layers as the first dielectric material layers, one of which being a high-k dielectric layer, and a gate conductor on and in contact with the second gate dielectric material layers, the second GAA FET including a second threshold voltage;
wherein:
the first and second channels have a thickness between about 4 nm and about 8 nm;
the first and second interfacial layers have a thickness between about 0.5 nm and about 1.5 nm;
the first dielectric material layers have a combined thickness between about 1 nm and about 3 nm;
the second vertical gate stack having diffused atoms of a metal from an anneal process; and
the first threshold voltage is different than the second threshold voltage.